S.NO | TITLE | PAGE NO | DOWNLOAD | |
IJATIR 11 | Implementation of High Performance 20-GHz RSFQ Multiplier Authors:VANDANA VARIPALLI, R.SATHYA VENI |
0060-0064 |
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IJATIR 12 | A Novel Improved Variable Step Size of Digital MPPT Controller For A Single Sensor in Photo Voltaic System Authors:K.MURALIDHAR REDDY, K.MEENENDRANATH REDDY, G.VENKATA SURESH BABU |
0065-0072 |
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IJATIR 13 | MDC FFT/IFFT Processor with Variable Length for MIMO-OFDM Systems Authors:VEMU SHIRDI SAIPRABHU, P.GOPALA REDDY |
0073-0081 |
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IJATIR 14 | UPQC-S: A Novel Concept of Simultaneous Voltage Sag/Swell and Load Reactive Power Compensations Utilizing Series Inverter of UPQC Authors:M.JASWANTH, M.PRASAD |
0082-0091 |
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IJATIR 15 | A Novel Single-Reference Six-Pulse-Modulation (SRSPM) Technique-Based Interleaved High-Frequency Three-Phase Inverter for Fuel Cell Vehicles Authors:SHAIK IRFAN, K. RAJESH KUMAR, M. MADHUSUDHAN REDDY |
0092-0100 |
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IJATIR 16 | Design and Implementation of OSN User Walls for Filter Unwanted Messages Authors:Y. YATHEESWARUDU, P. SUHASINI, K. GOVARDHAN REDDY |
0101-0107 |
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IJATIR 17 | Minimization of Fault Current & Overvoltage in a Distribution System Using Active SFCL Scheme with Wind Energy Based DG Units Authors:R. RAM PRASAD, B. MOHAN |
0108-0112 |
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IJATIR 18 | A Novel Improved Performance of Direct Power Control of Unified Power-Flow Controller Fed Induction Drive System Authors:K. VAJRALABABU, M. DEVIKA RANI |
0113-0119 |
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IJATIR 19 | Realization of UART Based Testable Circuits using Reversible Logic Authors:R. SRIDEVI, R. SATHYAVENI |
0120-0125 |
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IJATIR 20 | High Speed and Power Optimized Parallel Prefix Modulo Adders using Verilog Authors:MEDAPATI NANDINI, A. JAYAVANI |
0126-0133 |
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Submission Open for 2021 |
Last Date of Submission : |
20th, October-2021 |
Acceptance Notification : |
After Peer Review |
Last Date of Publication : |
30th, October-2021 |